title: "Sub-2nm Paradox: Why Smaller No Longer Means Better" description: "At 2nm and below, the semiconductor industry faces a fundamental contradiction - more transistors no longer guarantees better performance. Yield drops, costs rise, and the focus shifts from shrinking logic to data movement." tags: ["semiconductor", "chiplet", "advanced packaging", "GAA", "CFET", "Moore's Law", "AI chips"]
核心: 2nm 以下,晶体管越多 ≠ 性能越好。摩尔定律仍在延续,但游戏规则彻底改变了。 TL;DR: At 2nm and below, more transistors ≠ better performance. Moore's Law continues, but the rules of the game have fundamentally changed.
摩尔定律的裂缝 | The Crack in Moore's Law
理论上,在芯片上塞更多晶体管,就能处理更多数据、跑得更快。但理论和现实正在分道扬镳。
In theory, cramming more transistors onto a chip means faster data processing. But theory and reality are diverging.
2nm 以下,导线细到 RC 延迟成为重大挑战。SRAM 缩放远远落后于数字逻辑缩放。Fab 中因工艺变异导致的良率下降,让成本飙升。
At 2nm and below, wires are so thin that RC delay becomes a significant challenge. SRAM scaling falls way behind digital logic. Process variation in fabs drives yield down and costs up.
正如 Synopsys 工程副总裁 Abhijeet Chakraborty 所说:
"期望是尺寸缩小带来更快的性能、更低的功耗和更高的晶体管密度。但你能实现承诺的 10-15% 性能提升和 20-30% 功耗降低吗?这才是真正的挑战。"
"The expectation is that shrinking dimensions gives you faster performance, lower power, and higher density. But can you actually achieve that 10-15% performance gain and 20-30% power reduction? That's the real challenge."
工艺变异:看不见的敌人 | Process Variation: The Invisible Enemy
任何 Fab 都有工艺变异,但 2nm 以下,变异的来源和幅度都在急剧增加。
Every fab has process variation, but below 2nm, the sources and magnitude are exploding.
- 金属层翘曲 → 凸点不完全连接
- 数十道工序 → 每一步都可能损伤脆弱的互连
- 原材料和晶圆的批次差异 → 引入数百甚至数千个变异插入点
As proteanTecs CTO Evelyn Landman 指出:
"Margin 成为 2nm 和 18A 最受争夺的资源。把所有变异、热效应、老化因素加到一个静态保护带里已经不可行了。唯一可持续的方法是在真实工作负载下实时监控时序裕量。"
"Margin becomes the most contested resource at 2nm and 18A. Aggregating all variation, thermal effects, and aging into a single static guard-band is no longer viable. The only sustainable approach is real-time timing margin monitoring under real workloads."
CFET:晶体管叠罗汉 | CFET: Stacking Transistors Like Jenga
10A(即 1nm)之后,GAAFET 将让位于 CFET(互补场效应晶体管)。
After the 10A node (~1nm), gate-all-around FETs will give way to CFETs - Complementary Field-Effect Transistors.
图:CFET 架构 - N-FET 垂直堆叠在 P-FET 之上。来源:imec Fig: CFET architecture with N-FET vertically stacked on P-FET. Source: imec
Lam Research 首席 AI 官 David Fried 这样描述:
"从 planar 到 finFET 到 GAA,nFET 和 pFET 一直是横向排列。CFET 把它们上下叠在一起--这引入了前所未有的结构复杂性和互连复杂性。"
"From planar to finFET to GAA, nFETs and pFETs have always been lateral. CFETs stack them vertically - introducing structural complexity and interconnect complexity we've never seen before."
这意味着背面电源分配、光刻、材料选择......所有环节都要重新思考。
This means backside power distribution, lithography, material choices - everything needs rethinking.
Chiplet:当一颗芯片装不下 AI | Chiplets: When One Chip Can't Hold AI
AI 数据中心的需求让"把一切塞进一颗芯片"变得不可能。于是行业转向 多芯片组装(chiplet)。
AI data center demands make "cramming everything into one chip" impossible. The industry is shifting to multi-die chiplet assemblies.
图:封装技术从 2D → 2.5D → 2.xD → 3D 混合键合的演进。来源:Rapidus Fig: Packaging evolution from 2D → 2.5D → 2.xD → 3D hybrid bonding. Source: Rapidus
但这带来了新的难题:
But this brings new challenges:
| 技术 | 优势 | 挑战 |
|---|---|---|
| 2D FCBGA | 简单,成熟 | 互连密度低 |
| 2.5D 硅中介层 | 高带宽,chiplet 并排 | 硅中介层受 reticle 尺寸限制 |
| 2.xD RDL + Bridge | 灵活,可扩展 | 信号延迟 |
| 3D 混合键合 | 最高密度 | 散热,工艺变异叠加 |
Rapidus 封装技术 CTO Rozalia Beica 说：
"圆片在开始时更多用于 2.5D 硅中介层。但因为 reticle 尺寸限制，行业已经开始向面板转移。面板产能更高。"
"Round wafers will be used more for 2.5D silicon interposers initially. But due to reticle size limits, the industry is already moving to panels. Panels have higher capacity."
面板级封装（500×500mm）是下一个大趋势——用矩形基板代替圆形晶圆，提高芯片产出率。但这也意味着全新的设备和处理工艺。
Panel-level packaging (500×500mm) is the next big trend — rectangular panels replacing round wafers for higher chip yield. But this means entirely new equipment and handling processes.
定制化时代 | The Era of Customization
在 2nm 以下，没有"通用"芯片了。每家 foundry 都在提供定制化方案：
At 2nm and below, there's no such thing as a "one-size-fits-all" chip. Each foundry is offering customization:
- Intel Foundry: 基础层统一，上层金属可定制，还有 bridge 互连选项
- TSMC: NanoFlex 标准单元架构，灵活搭配
- Samsung: 定制 HBM，从内存角度提升性能
- Rapidus: die-on-wafer 和 die-on-panel 方案
proteanTecs 的 Landman 总结得好：
"会有通用平台，但有意义的定制仍将持续。不同市场看重不同的权衡。随着定制化增加，设计意图、硅片现实、封装行为和系统操作之间的快速关联变得至关重要。"
"There will be common platforms, but meaningful customization will remain. Different markets value different tradeoffs. As customization increases, fast correlation between design intent, silicon reality, package behavior, and system operation becomes critical."
材料创新：从钨到钼，从电到光 | Material Innovation: From Tungsten to Molybdenum, From Electrical to Optical
Lam Research 的 Fried 指出，材料创新正在加速：
Lam Research's Fried points out that material innovation is accelerating:
- 钨 → 钼：已在 NAND 和 DRAM 字线和低层逻辑互连中发生
- 钴 → 钌：即将在低层互连和布线中应用
- 集成光子学：AI 系统推动了对玻璃基板中光波导的关注
- High-NA EUV：Intel 14A 正在探索用单次曝光替代多次曝光，简化工艺流
从电到光的转变可能是最深刻的——玻璃基板中的光波导可以加速数据传输，同时几乎不增加热量。
The shift from electrical to optical may be the most profound — optical waveguides in glass substrates can accelerate data movement with almost no additional heat.
结论：超越摩尔的真正含义 | Conclusion: What "More-than-Moore" Really Means
这篇文章的核心观点可以用一句话概括：
The core message in one sentence:
2nm 以下，竞争不再是谁的晶体管更小，而是谁能更好地移动数据。
Below 2nm, the competition is no longer about whose transistors are smaller, but who can move data better.
摩尔定律没有死——它只是换了赛道。
- 从平面缩放 → 3D 堆叠
- 从单芯片 → chiplet 组装
- 从电互连 → 光互连
- 从通用芯片 → 定制化方案
- 从"更多晶体管" → "更好的数据流"
Moore's Law isn't dead — it just changed lanes.
- From planar scaling → 3D stacking
- From monolithic chips → chiplet assemblies
- From electrical interconnects → optical interconnects
- From general-purpose chips → customized solutions
- From "more transistors" → "better data flow"
正如 Lam Research 的 Fried 所说：
"我们仍然在做平面加工——把晶圆放进设备，处理暴露的表面。每个工艺都有参数、变异和测量技术。这些都会渗入你构建的结构中。但现在有更多的工艺、参数和关键性能指标。理解这些变异如何传播的数学原理没有改变。"
"We're still doing planar processing — putting a wafer into equipment and processing whatever is exposed. Every process has parameters, variability, and measurement techniques. That seeps into whatever structure you're building. But now there are more processes, parameters, and KPIs. The math hasn't changed for understanding how those variabilities propagate."
本文基于 SemiEngineering 文章 The Sub-2nm Paradox 编译分析，图片来源 imec 和 Rapidus。
This article is based on analysis of the SemiEngineering piece The Sub-2nm Paradox, with images sourced from imec and Rapidus.
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